In the prior art, microprocessors have utilized bus and buffer configurations for distributing ALU results to various points therein. Such results have required several microprocessor machine cycles. The following examples illustrate this diversity.
The article "Microprogramming: Perspective and Status" by A. K. Agrawala et al., published in IEEE Transactions on Computers, Vol. C-23, No. 8, August 1974, pp. 817-837 is a survey of several processor designs. In FIG. 11 of this article, a processor is shown in which the ALU output is connected through a shifter to a data bus to which also several working registers and a memory data register are attached. Working register outputs are connected to ALU inputs by means of additional data buses. In FIG. 13 showing another processor, the ALU output bus is connected directly to general registers, through a shifter to an ALU input bus, and to a main memory data bus. General register outputs are connected either directly or through a shifter to the ALU inputs via data buses. In both processors, memory addresses and data must be transferred over the same ALU output bus.
An article by H.-M. D. Toong "Microprocessors", published in Scientific American, September 1977, pp. 146-161, shows a similar arrangement. It has only a single common data bus which is used for both, data and addresses. ALU results are returned to the accumulator.
U.S. Pat. Nos. 4,047,247 and 4,079,451 disclose data processing systems in which data paths are provided for connecting the output of an adder to an internal bus and via a multiplexer/shifter to several working registers, and for connecting the internal data bus and the working registers to inputs of the adder. The memory is connected to an external bus via the internal bus but both, data and addresses must be transferred to the memory over the same internal bus.
In the Intel MCS-85 User's Manual, published September 1978, a block diagram of the 8085 A CPU is shown in FIG. 2-1. It includes an ALU whose output is connected via an internal data bus to two working registers associated with the ALU inputs, and to a register array. Buffers separate the internal data bus from the memory data and address bus.
A signal processor is described in the publications "V-MOS chip joins microprocessor to handle signals in real time" by R. W. Blasco, Electronics, Aug. 30, 1979, pp. 131-138, and "Schnelles Rechenwerk erweitert Mikroprozessor-Systeme" W" by W. E. Nicholson et al., Elektronik 1979, No. 4, pp. 53-60. In this processor, the output of an adder/subtractor is always stored into an accumulator. Contents of the accumulator can be transferred to a memory or to a scratchpad, via a shifter to one input of the adder/subtractor, and to a multiplier whose output is connected to the other adder/subtractor input. Data paths are provided from the memory to the multiplier and to both adder/subtractor inputs.
Chung, U.S. Pat. No. 4,086,626, issued Apr. 25, 1978, discloses and claims a microprocessor formed from a unitary CPU chip absent a program counter and at least one unitary RAM chip including a program counter. A multimemory configuration permits multiprocessing using a single clock since instruction streams can be drawn from each RAM whose extraction cycle is controlled by strobing the local program counter from the single clock.